Accumulation field effect microelectronic device and process for the formation thereof

ABSTRACT

A gated microelectronic device is provided that has a source with a source ohmic contact with the source characterized by a source dopant type and concentration. A drain with a drain ohmic contact with the drain characterized by a drain dopant type and concentration. An intermediate channel portion characterized by a channel portion dopant type and concentration. An insulative dielectric is in contact with the channel portion and overlaid in turn by a gate. A gate contact applies a gate voltage bias to control charge carrier accumulation and depletion in the underlying channel portion. This channel portion has a dimension normal to the gate which is fully depleted in the off-state. The dopant type is the same across the source, drain and the channel portion of the device. The device on-state current is determined by the doping and, unlike a MOSFET, is not directly proportional to device capacitance.

REFERENCE TO RELATED APPLICATIONS

This application is a continuation-in-part of U.S. patent applicationSer. No. 12/102,398 filed Apr. 14, 2008, that in turn claims priority ofU.S. Provisional Application Ser. No. 60/911,378 filed Apr. 12, 2007 andU.S. Provisional Application Ser. No. 60/951,547 filed Jul. 24, 2007;the contents of all of which are incorporated herein by reference.

STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

This invention was made with government support under Grant No.DMI0615579, awarded by the National Science Foundation. The Governmenthas certain rights in the invention.

FIELD OF THE INVENTION

The present invention relates in general to field effect microelectronicdevices and in particular to a field effect device having asubstantially single dopant type across source, gated intermediateportion, and drain.

BACKGROUND OF THE INVENTION

A conventional metal oxide semiconductor field effect transistor(MOSFET) utilizes heavily doped source and drain semiconductor regionsto form ohmic contacts to a gate induced inversion-layer channelportion. In the on-state, transport in this channel portion controls thesource-drain current, I_(DS). In the on-state, the inverted channel isnot shunted due to the presence of a reversed-biased n/p or p/n junctionat the drain. In the off-state there is no inversion in the channelportion and the current, I_(D) is blocked by the reverse biased n/p orp/n junction at the drain. The thin film transistor (TFT) is a variantof the MOSFET in which an on-state conducting channel is also notshunted but, in this case, due to a reversed bias i/n or i/p junction atthe drain which is in series with the additional impediment of the thin,resistive i-layer under the gate. Both TFTs and MOSFETs are types offield effect transistor (FET) structures.

A typical FET device includes a gate, drain, and source. Typically, thegate is used to control the device by applying an adequate voltage tothe gate to generate an electric field that in turn creates a conductivepath in an underlying channel layer intermediate between the drain andsource. A device in which conduction exists between the source and drainis considered to be ins an on-state whereas a lack of conduction isconsidered as an off-state.

The gate, the third terminal of these devices, needs to be electricallyisolated from the channel layer. To achieve electrical isolation of thegate, a dielectric material such as silicon dioxide is providedintermediate between the gate and the underlying channel layer. Toimprove device characteristics it is often desired to reduce thedielectric (insulator) layer thickness to increase gate capacitance andimprove gate to channel coupling. An inverse proportionality exists forMOSFET and TFT type devices between the gate capacitance and insulatinglayer thickness. Unfortunately, reducing insulating layer thicknessbeyond a certain point has proven difficult as gate leakage currentoutweighs any benefits achieved through gate capacitance increases.

The trend in microelectronics is to ever smaller devices since thisallows for faster operating speeds and greater functionality per area.Fabricating such small devices can be costly since the processinginvolved generally necessitates multiple etching and deposition stepsall guided by lithography. Nanowires, nanotubes, and nanoribbons areinherently small; hence there is a great deal of interest in fabricatingFET devices using these materials.

FET structures that can be fabricated with the dimension normal to thegate being in the nanoscale include TFTs on ultra-thin semiconductors,SOI-type structures, thin-fin devices and nanowire devices. Among thesepossibilities, devices with a single doping type have been fabricatedusing nanowires (NWs) by Lieber et al.^(5,6,7), Mayer et al.⁸, and Yanget al.⁹ These have used semiconductor nanowires of a single doping typeand concentration, ohmic source and drain contacts to thissemiconductor, and metal/insulator gates and have been professed to beMOSFETs^(5,6,7,8,9). These prior art devices have stressed theimportance of gate capacitance, C_(I) in on-state operation. The priorart has not taught the role of doping concentration on on-state current,has not taught the importance of the position of ohmic contacts withrespect to channel edges, the correct role of C_(I) in on-stateoperation, nor the role of the doping concentration in the variousregions of the transistor on performance of single doping-type FETs. Therole of the voltage V_(DS) developed between the source and drain in asingle doping type structure has not be realized and there has been alacking of guidance as to device design. In fact, Mayer et al. hasstrongly taught away from NW FET structures with single doping typeciting that they are not capable of good on-current to off-currentratios nor of good subthreshold slopes (swing) values.⁸ Thus, thereexists a need for a gated microstructure that is simple to fabricate andhas straightforward design rules. Using a single doping type for thesource, gate, and drain regions, as disclosed in this invention, is amajor simplification step as is the disclosed use of substantially ohmiccontacts to the source and drain regions. Further, having a FET devicewhose dependence on gate capacitance is weaker than that of a MOSFETovercomes the problem of the need for close fabrication control of thegate insulator. There also exists a need for a simplified formation ofFET-type structure to advance the operation of microelctronics andmacroelectronics (electronics applied to large areas).

SUMMARY OF THE INVENTION

A gated microelectronic device is provided that has an ohmic contact toa source semiconductor region characterized by a source dopant type andconcentration and linear extent. There is also an ohmic contact to adrain semiconductor region which is characterized by a drain dopant typeand concentration and linear extent. A voltage is imposed in operationbetween the drain and the source. A channel portion intermediate betweenthe source and the drain is characterized by a channel portion dopanttype and concentration and defines a channel portion linear extent and achannel portion thickness. An insulative dielectric is in contact withthe channel portion and overlaid in turn by a gate. A gate contactapplies a gate voltage bias to control charge carrier accumulation anddepletion in the underlying channel portion. The dopant type is the sameacross the source, drain and the channel portion of the device.Ambipolar behavior of the device is prevented by dimensional and dopantconcentration level selections. The device exhibits FET behavior with anon-state when accumulated and an off-state when depleted.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a cross-sectional schematic of an inventive device withfunctionally inactive portions such as a substrate and passivatinglayers not being shown for visual clarity;

FIG. 1B is a schematic depicting the inventive device of FIG. 1A withelectrical contacts of the drain and gate biased relative to the sourceso as to place the device in an off-state configuration;

FIG. 1C is a schematic depicting the inventive device of FIG. 1 A withelectrical contacts of the drain and gate biased relative to the sourceso as to place the device in the on-state configuration;

FIG. 2A is a plot of experimental source drain current I_(DS) as afunction of voltage V_(DS) for different applied gate bias values V_(G)for the inventive device depicted in FIG. 1;

FIG. 2B is a plot of experimental source drain current I_(DS) as afunction of applied gate bias V_(G) with V_(DS)=−0.1V for the inventivedevice depicted in FIG. 1;

FIGS. 3A-3D depict a construction technique as perspective views for aninventive device according to techniques detailed in United StatesPatent Application Publication US 2005/0176228 A1;

FIGS. 3E and 3F are field effect scanning electron micrographs (FESEMs)of several inventive devices;

FIGS. 4A-4D are partially transparent schematic representations of stepsassociated with the use of growth channel input transfer for a longchannel template;

FIGS. 5A-5D are partially transparent schematic representations of stepsassociated with the use of growth channel input transfer for a shortchannel template; and

FIG. 6 is a top view schematic of an inventive NOT AND (NAND) gatedevice.

DESCRIPTION OF THE INVENTION

The present invention has utility as a microelectronic device. Aninventive device is an accumulation type MOSFET and relies on theformation of a charge carrier accumulation layer and channel portionunder the gate to create a conductive on-state. The inventive device issimple to fabricate as a single dopant type is used across source,channel portion, and drain. Single dopant type is either an n-type orp-type dopant. To further simplify fabrication, an inventive device alsooptionally has a uniform dopant concentration of single dopant typeacross the source (region I of FIG. 1), channel portion (region II ofFIG. 1), and drain (region III of FIG. 1). In operation, an inventivedevice operates by way of the volume of the channel portion under thedate accumulating (on-state) or depleting (off-state) charge carriersthereby switching between conduction and isolation between the sourceand drain, respectively. For an inventive device to function as atransistor, in the off-state, the charge carrier depletion within achannel portion must occupy the complete depth of the channel portionunder the gate so as to preclude leakage between source and drain. As aresult, the channel portion in an inventive device has an ultra thinsemiconductor. More generally, the dimension normal to the gate isultra-thin.

As used herein “ultra thin” is defined as being capable of beingdepleted of charge carriers under the appropriate gate bias; i.e.,depleted under positive gate bias for p-type doping and depleted undernegative gate bias for n-type doping. Typically, the ultra thinsemiconductor has a dimension normal to the gate (e.g., diameter of ananowire, thickness of a thin film) of less than 100 nanometers and morethan 5 nanometers and preferably less than 80 nanometers.

An ultra thin semiconductor channel portion according to the presentinvention can be readily formed from the silicon of silicon-on-insulatorstructures, from semiconductor thin films such as those typically formedby techniques such as physical vapor deposition, chemical vapordeposition, and atomic layer deposition techniques, and fromsemiconductor nanowires, nanoribbons, and nanotubes, where nanotubesdefine a hollow shell as opposed to a filled core nanowire. Thesemiconductor thin films and nanowires, nanoribbons, and nanotubes canbe comprised of a variety of materials illustratively including carbon,germanium, silicon, II-VI semiconductors, III-V semiconductors, andmixtures and layered structures thereof

This inventive device class, herein synonymously termed an AMOSFET(accumulation metal oxide semiconductor field effect transistor),affords a number of operational and fabrication advantages overconventional MOSFETs and TFTs. These advantages include a simplicity offabrication being operational with a single doping type across source,channel portion, and drain and with only requiring ohmic contacts to thesource and drain regions as seen in FIG. 1. An inventive device operateswith dopant concentrations of between 10¹² per cm³ and 10¹⁹ per cm³ andpreferably at between 10¹⁴ per cm³ and 10¹⁸ per cm³. The presence ofohmic contacts separated from the edges of the channel region as seen inFIG. 1 means that an inventive device can operate without ambipolarbehavior. Another unique aspect of the AMOSFET is that the dependence ofits current-voltage (I-V) behavior on gate capacitance is much less thanthat seen for MOSFETs and TFTs.

A related similar device developed subsequent to the present inventionby Byon et al.²³ used ohmic contacts and one doping type silicon NWs inan accumulation type FET but did not use the innovation of positioningthe ohmic contacts away from the channel edges. As a consequence, thisother device exhibits ambipolar behavior (i.e., with p-type doping itinverts under positive gate bias instead of depleting only) which can bevery deleterious in circuit applications. In contrast, the inventivedevice has the properties and the positioning of the ohmic contacts thateliminate ambipolar behavior or, alternatively, if it is desired,optionally attain ambipolar behavior in a single doping type FET.

To eliminate ambipolar behavior, the ohmic contacts in the inventivedevice of FIG. 1 are separated from the channel edges and arenon-contiguous therewith. These contacts are substantially ohmic givingno significant voltage drop while passing current and unable to supplythe necessary significant minority carrier injection needed to createand sustain an inversion layer In any case, the dimensional extent ofregions I and III are such that, under gate biasing that is conducive toinversion layer formation, the minority carrier density in the portionof these regions near the channel edges cannot differ significantly fromthat present in thermodynamic equilibrium insuring a sustained inversionlayer can not be developed.

Additionally, an inventive device ameliorates the need for close controlof the thickness of the dielectric insulating the gate from theunderlying channel portion since on-state current depends on materialdoping and is not directly proportional to gate capacitance, C_(I),which it is in MOSFETs and TFTs, Additionally the voltage drop betweensource and drain can be readily integrated into local interconnects andformation of a very-large-scale integration (VLSI); i.e., the source anddrain regions can be part of the interconnects, if desired. As aconsequence of the weak dependence on the insulating dielectricthickness underlying a gate, device performance problems associated withquantum mechanical carrier tunneling through the gate dielectric can belargely circumvented.

The structure and operation of an inventive device operating as anaccumulation MOSFET is provided in FIGS. 1A-C. While the description ofthe present invention that follows details for illustrative purposes awholly p-type doped device based on a silicon nanowire operational asthe ultra thin semiconductor, it is appreciated that the other ultrathin semiconductors such as those possible in TFT and SOIconfigurations, as well as other nanotubes, nanoribbons, and nanowirematerials, are also operative herein. It is understood that a device canbe wholly p or n-type and that doping concentration can be essentiallyconstant or varied across a device. FIGS. 1A-C show in region I a p-typedoped semiconductor source region in region I (S of FIG. 1A) and aregion III also p-type doped constituting a semiconductor drain (D ofFIG. 1A). Region II corresponds to a channel portion of p-type doping onwhich are applied an insulative dielectric and a gate thereover. RegionsI, II and III have the same doping type which may vary in concentrationacross the device. For example, the doping concentration may be chosento be larger in the source-drain regions than under the gate or viceversa.

In an off-state as depicted in FIG. 1B, a bias is applied to the gate byway of a contact to deplete region II corresponding to the channelportion so as to deplete the channel portion of charge carriers and as aresult only a nominal drain current can flow when the drain voltageV_(DS)<0 is applied between the drain and source. It is appreciated thatwith n-type doping opposite polarity gate biases are applied to gateinduce an off-state. According to an inventive device, the semiconductorof the channel portion (region II) cannot readily invert in off-statebiasing due to the adjacent p-type source and drain regions (regions Iand III, respectively). In the event that inversion were to occur in thechannel portion (region II), charge carrier transport in the resultinginversion layer would be limited by reverse bias p-region contactingthis inversion layer.

In the on-state, as depicted in FIG. 1C, a sufficient negative gate biasV_(G)<0 region II accumulates charge carriers and a drain current, I_(D)flows when the drain voltage V_(DS)<0 applied between the drain andsource. Since region II is accumulated, I_(D) before saturation must beprincipally a drift current. Taking all three regions (I, II, and III)to have the same doping type and same linear extent L_(G), for example,I_(D) before saturation can be approximately modeled asI _(D) =eN _(A)μ_(p) V _(A) /L _(G)   (1)where N_(A) is the semiconductor doping density, μ_(p) is its holemobility, and V_(A) is a voltage obeying IV_(A)I≦IY_(DS)I. Eq. (1) in anapproximate description of the linear section of the outputcharacteristics such as that seen in the experimental data plotted inFIG. 2A. This equation points out that this region of the outputcharacteristics of an inventive device is controlled by the doping N_(A)and not by the gate capacitance C_(I) per area as is the case in atraditional MOSFET. This equation further shows that I_(D) in the linearregion is on of the order of the current which would flow for the sameV_(DS). These features of linear dependence on doping and lack ofMOSFET-like dependence on gate capacitance have been substantiated bydetailed AMOSFET numerical modeling.²⁴ As shown also in that detailedAMOSFET numerical modeling, the saturation behavior in a p-type dopeddevice, for example, arises from the pulling of holes primarily out ofregion II. The output and transfer characteristics that result from theoverall linear and saturation regions behavior are those of a“conventional” MOSFET or TFT as seen in the experimental data of FIGS. 2a and 2 b.

An inventive device functions due to an ultra thin semiconductor channelportion of this one-doping-type device and the switching that occursbased on carrier accumulation in the on-state, and carrier depletion inthe off-state of this channel portion. The doping concentrations inregions I and III are optionally changed from that of region II, butunlike a MOSFET, the doping type cannot be changed. Ambipolar behavior,synonymously detailed as an inversion layer formation in what should bethe off-state, is precluded by ohmicity of the source and drain contactsand the linear extent of regions I and III, these being such that theminority carrier density in the portion of these regions I and III nearthe channel edges of region II does not differ significantly (i.e., notable to sustain an inversion region) from that present in thermodynamicequilibrium. It is appreciated that linear extent takes into account theinterchanging of the roles of source and drain. This linear extent Lwill depend on the quality of the ohmic contacts and can be determinedexperimentally by determining the linear extent needed to stop ambipolarbehavior. Preferably, both regions I and III have linear extents ofgreater than or at least equal to that necessary to avoid sustainedinversion layer creation in region II. Alternatively, ambipolar behavioris achieved by making the linear extents of regions I and III equal toor less than that necessary for sustained inversion layer creation inregion II.

It is appreciated that through coupling of n-type and p-type AMOSFETshooked up in series, multiple inventive devices act reciprocally as theload for each other to construct logic circuits and other VLSIcomponents.

A Dual-gated AMOSFET is optionally formed with two gate regions betweenthe source and drain ohmic contacts as shown in FIG. 6. A 4-terminaldevice, with gates G1 and G2, along with source S and drain D isprovided. With two independent input signals applied to G1 and G2, thedevice will turn ON only when both G1 and G2 are HIGH. With a normalresistive load at the drain, this gives a NOT AND (NAND) gate operation.Such a configuration with conventional transistors would suffer fromcomplications of level shifting between the two gate signals, but it canbe possible to avert this with the AMOSFET due to the entirely differentoperating principles. For instance, the nanowire mid-region between thetwo gates is controlled both in geometry and dopant concentration. It isappreciated that any number of gates may be stacked, yet preferably thenumber of gates is limited to two.

Alternatively, the dual-gated device of FIG. 6 is operated with a singleinput; i.e. with gates G1 and G2 shorted. The purpose of this is toalter the device characteristics by controlling the length of themid-region. The device in this operational mode functions as a lightsensor with a beam of light incident on the mid-region altering thepotential distribution along the length of the nanowire and affordingphotogain.

An inventive device can be readily used for a number of applicationsincluding such diverse examples as pixel control, sensing, andelectro-static discharge control. An inventive device can form variouscircuit elements. Its particularly simple configuration can allow suchelements to be uniquely attained. For example, a NOT AND (NAND) gatedevice can be made with a uniformly doped ultra thin semiconductorchannel portion of one doping type and the inclusion of four ohmiccontacts.

To further appreciate fabrication and operating performance of aninventive device, reference is made to the following nonlimiting examplewhich are intended to illustrate specific exemplary devices and not tolimit the interpretation or scope of the appended claims.

Example 1 AMOSFET Fabricated Using a Template on a Substrate

An inventive device is fabricated using silicon nanowire material. Thenanowires are grown on a substrate and transistors fabricated in situ.No transfer process is utilized. An inventive device fabrication beganwith the vapor-liquid-solid (VLS), grow-in-place silicon nanowire (SiNW)growth process in growth channels approach previously detained in U.S.Patent Application Publication 2005/0176228.

In the grow-in-place variation used here, Corning 1737 glass, serves asthe substrate on which the permanent growth-templates are constructed.Template construction is known^(2,4) and the use of such templates issummarized in FIG. 3 for the fabrication of the inventive devices ofthis example. The resulting permanent templates are designed to allowvapor-liquid-solid (VLS) nanowire growth in, and then finally extrusionout of, the guiding nanochannels under the capping layer of FIG. 3 inthe particular version of grow-in-place used herein. In other versions,the transistor can be fabricated on a nanowire confined in the template(See Yinghui Shan and Stephen J. Fonash, “Self-Assembling SiliconNanowires for Device Applications Using the Nanochannel-Guided“Grow-inPlace” Approach”, American Chemical Society, Published onlineFeb. 22, 2008, 10.1021/nn700232q CCC.) Using extruded wires forfabricating transistor is seen in the micrographs of FIGS. 3E and 3F.Other grow-in-place procedures operative herein are also discussed inU.S. Patent Application Publication 2005/0176228. This silicon nanowireVLS growth is carried out in a liquid precursor chemical vapordeposition (LPCVD) reactor at 500° C. and 13 Torr, using 5% SiH₄ dilutedin H₂ with a total flow rate of 100 sccm^(2,10). The grow-in-placeapproach produced SiNWs positioned where desired on the substrate. Thesewires are held at the template end by the channels of the permanenttemplates as shown in the sequence of FIGS. 3A-3D and, as seen,fabricated into devices.

After the nanowire growth, the residual gold used to catalyze the VLSprocess is completely removed by rinsing the whole sample in goldetchant following by deionized (DI) water cleaning. Other VLS catalystssuch as Ti, for example, are also operative herein. The siliconnanowires are subsequently subjected to a modified standard cleaning.Prior art^(2,11) indicates that this Si material grown by thegold-catalyzed VLS process is p-type due to inadvertent Au doping duringthe VLS process. Transistor structures are then made in situ.Thereafter, an HF etch, a wrap-around encapsulating SiO₂ layer is grownby dry thermal oxidation at 700° C. for 4 hours using a 3 L/min O₂ flowrate^(8,12,13). This oxidation resulted in a Si/SiO₂ core-shellstructure^(8,12,14,15) with about a 10 nm thermal silicon oxidesurrounding the silicon nanowires. This oxide is removed in selectedsource/drain contact regions using standard processing and the contactmetals (400 nm Ti/50 nm Au) are deposited with the Ti contacting thesilicon nanowires, followed by lift-off. The gates of the siliconnanowire transistor structures are then patterned and formed bydepositing the Ti (400 nm)/Au (50 nm) on the gate oxide. From FESEMstudies, the diameter of the resulting silicon nanowire transistorstructures with their wrap-around oxide is about 75 nm, with the actualsilicon nanowire having a diameter of about 55 nm and a surrounding 10nm thick oxide shell. These transistors had 2 μm gate length (LG) and2.5 μm gate-source/gate-drain spacings, with a source length of 2.5 μmand a drain length of 2.5 μm.

The performance of the inventive device structures fabricated using thegrow-in-place silicon nanowires was evaluated using an Agilent 4156Precision Semiconductor Parameter Analyzer and results are presented inFIG. 2. Single silicon nanowire transistor structures are employed inthe evaluation. The plot of FIG. 2A gives the measured outputcharacteristics for a typical grow-in-place SiNW transistor for valuesof the gate voltage V_(G) stepped from 0.5V (bottom) to −1.5V (top) in−0.25V increments. Each I_(D)−V_(DS) curve (e.g., the curve forV_(G)=−1.5 V) shows that the drain current absolute value |I_(D)| firstincreases and then saturates, as observed for a conventional MOSFET. Thecorresponding measured transfer characteristics with V_(DS) fixed at−0.1 V are shown in FIG. 2B as the semi-log plot along with a linearplot of I_(D) versus V_(G) (scale on the left ordinate) for determiningthe threshold voltage. From the semi-log plot, which is also typical ofthat observed for a conventional MOSFET, the device is seen to have anon/off ratio of 10⁶ and a subthreshold slope (SS) of 130 mV/dec.Although this latter value is approximately double the best value insingle crystal silicon devices (70 mV per decade)¹⁶, this subthresholdslope appears to be the lowest value ever reported for a single top-gateor bottom-gate nanowire device and is much lower than the typical values(>300 mV/dec) reported for single, top-gate or bottom-gate nanowiredevices.^(7,17,18,19) This SS is also comparable to the best value (120mV/dec) seen for vertical silicon nanowire array devices⁹. In addition,this value is lower than the best values reported for poly-Si TFTs (200mV per decade).²⁰

The data of FIG. 2B show that an inventive device structure of thisexample has an off-state with positive gate voltages, turn-on withnegative gate voltages, and has a threshold voltage of about −0.6V.Without intending to be bound by a particular theory, it is seen thatthe carriers in the on-state are holes and that the on-state behavior isdue to a hole accumulation layer in region II for negative gatevoltages. It follows that the off-state of these transistors is producedby fully depleting the ultra thin semiconductor of charge carriers, asituation which is easily attained due to the nanoscale cross-sectionaldimensions thereof. The experimental data of FIG. 2B make it clear thatambipolar behavior was not present in the devices of this example.

Example 2 Growth Channel Template Transfer and Stamp Technique

The growth channel template method utilized with a transfer approach isdetailed for also producing an inventive device. FIGS. 4A-D and FIGS.5A-D show the schematic representations of the use of the growth channeltemplates with a transfer approach. These growth channel templates aremade on a mother substrate. Two versions of channel templates are shown:a long/encapsulated channel template (FIG. 4) and a short channeltemplate (FIG. 5). These both show the channel template transfer afternanowire growth from a mother substrate to a flexible substrate.Inventive device fabrication is completed either before or aftertransfer. Growth channel templates can also be transferred from themother substrate to the final substrate before nanowire, nanoribbon ornanotube growth in the same way. When done in this manner, fulltransistor fabrication is done after wire/ribbon growth transfer, withnanowire, nanoribbon or nanotube growth being done using the growthchannel templates after the templates are positioned on the finalsubstrate. In this channel template transfer technique, “grow-in-place”approach and the channel template transfer techniques for devicefabrication are combined on diverse substrates, such as flexiblesubstrates. The channel template including the long channel template orshort template could be fabricated on a mother substrate such as asilicon, a metal, or glass substrate covered with a sacrificial layer(e.g., silicon oxide) and channel template floor layer (e.g., siliconnitride) on the substrate (FIGS. 4A and 5A). The sacrificial layer(e.g., silicon oxide) serves as the sacrificial material for the channeltemplate release and the floor layer serves as the supporting floor ofthe template during template transfer. The channel template isfabricated on this sandwich structure as described in U.S. PatentApplication Publication 2005/0176228 and other sources.² After thenanochannel template fabrication on the mother substrate, the templateis transferred to a final substrate before or after nanowire growth. Ifthe template transfer is done to a final high temperature stablesubstrate, the growth channel template is transferred before or afternanowire growth. If the template transfer is to a final substrate, suchas plastic substrate, that is not stable at high temperatures, it isnecessary to grow the nanowires, nanoribbons or nanotubes on the mothersubstrate first and then the template with the silicon nanowires,nanoribbons or nanotubes is transferred to the new substrate. A transferlayer is optionally applied on the channel template shown in FIGS. 4Band 5B. The transfer layer is formed from a variety of materialsillustratively including polydimethyl siloxane. The sacrificial layer isreadily removed by processing techniques illustratively includingetching, ablation, agitation or a combination thereof in order torelease the structures. The released structure shown in FIGS. 4C and 5Cis transferred and stamped at desired positions onto differentsubstrates, such as plastic substrates (FIGS. 4D and 5D). The transferlayer is then optionally removed. This growth channel template andtransfer/stamp approach is very different from the transfer/stampapproach of Rogers et al.^(21,22) The approach here does not useexpensive SOI substrates as the mother substrate and instead grows thesemiconductor using a catalyst technique such as the VLS method ingrowth channel templates. This growth step is optionally accomplished ona mother substrate and the mother substrates of this approach are bothinexpensive and/or reusable.

Example 3 Thin Film Transistor Fabrication

As discussed above, an inventive device can be fabricated using ultrathin film semiconductors. These are deposited and defined, for example,by etching or are grown nanoribbons produced, for example, by thepreviously discussed VLS grown-in-place method. Unlike conventional TFTtransitory, AMOSFETs fabricated with thin film semiconductors use filmsof only one doping type (and not n/i/n or p/i/p dopings) and the dopingconcentration is crucial in determining the on-current magnitude. As isalso characteristic of AMOSFET devices, the on-current is notproportional to gate capacitance and gate insulator thickness controlneed not be of paramount concern.

Example 6 AMOSFETs Using SOI

High quality silicon on insulator type semiconductor materials is usedto fabricate AMOSFETs. Unlike conventional SOI transitors, AMOSFETsfabricated with such film use only one doping type and the dopingconcentration is crucial in determining the on-current magnitude. As isalso characteristic of AMOSFET devices, the on-current is notproportional to gate capacitance and gate insulator thickness controlneed not be of paramount concern.

References Cited

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Patent documents and publications mentioned in the specification areindicative of the levels of those skilled in the art to which theinvention pertains. These documents and publications are incorporatedherein by reference to the same extent as if each individual document orpublication was specifically and individually incorporated herein byreference.

The foregoing description is illustrative of particular embodiments ofthe invention, but is not meant to be a limitation upon the practicethereof. The following claims, including all equivalents thereof, areintended to define the scope of the invention.

The invention claimed is:
 1. A gated microelectronic device comprising:an insulator substrate; a source supported on said insulator substrate,said source having a first metal contact defining a first ohmic contactinterface with said source, said source having a source dopant type anda source dopant concentration and defining a source linear extent; asemiconducting drain supported on said insulator substrate, saidsemiconducting drain having a second metal contact defining a secondohmic contact interface with said semiconducting drain, saidsemiconducting drain having a drain dopant type and drain dopantconcentration and defining a drain linear extent; a channel portionintermediate between said source and said semiconducting drain, saidchannel portion supported on said insulator substrate and having achannel portion dopant type and channel portion dopant concentration anddefining a channel portion linear extent and a channel portionthickness, at least said channel portion being a semiconducting nanowireor a nanotube; an insulative dielectric in contact with said channelportion; a gate in overlying contact with said insulative dielectric,said gate defining a gate-insulative dielectric interface; said channelportion having a dimension normal to the gate-insulative dielectricinterface suitable to fully deplete in an off-state; a gate contactapplying a gate voltage bias to control charge carrier accumulation anddepletion in said channel portion; and the source dopant, the draindopant, and the channel portion dopant being all of a same type; andwherein the first ohmic contact interface is noncontiguous with saidchannel portion and the source linear extent, the drain linear extent,and the positioning of the first ohmic contact interface and the secondohmic contact interface prevent ambipolar behavior in the device.
 2. Thedevice of claim 1 wherein the doping type is p-type and the gate voltagebias is negative and the drain voltage bias is negative to yield adevice on-state status.
 3. The device of claim 1 wherein the doping typeis p-type and the gate voltage bias is positive and the drain voltagebias is negative to yield a device off-state status.
 4. The device ofclaim 1 wherein the doping type is n-type and the gate voltage bias ispositive and the drain voltage bias is positive to yield a deviceon-state status.
 5. The device of claim 1 wherein the doping type isn-type and the gate voltage bias is negative and the drain voltage biasis positive to yield a device off-state status.
 6. The device of claim 1wherein the dimension of said channel region normal to the gate isbetween 5 and 100 nanometers.
 7. The device of claim 1 wherein saidchannel portion is formed from organic semiconductors or inorganicsemiconductors.
 8. The device of claim 1 further comprising a secondgate intermediate between said source and said semiconducting drain. 9.The device of claim 1 wherein said insulative dielectric forms awrap-around contact with said channel portion.
 10. The device of claim 1wherein the channel portion is formed from one of: silicon, germanium,II-VI semiconductors, III-V semiconductors, or carbon.
 11. A gatedmicroelectronic device comprising: a source having a first metal contactdefining a first ohmic contact interface with said source, said sourcehaving a source dopant type and defining a source linear extent; asemiconducting drain having a second metal contact defining a secondohmic contact interface with said semiconducting drain, saidsemiconducting drain having a drain dopant type and drain dopantconcentration and defining a drain linear extent; a channel portionintermediate between said source and said semiconducting drain, saidchannel portion supported on an insulator substrate and having a channelportion dopant type and defining a channel portion linear extent and achannel portion thickness, said channel portion being a nano wire or ananotube; an insulative dielectric in contact with said channel portion;a gate in overlying contact with said insulative dielectric, said gatedefining a gate-insulative dielectric interface; said channel portionhaving a dimension normal to the gate-insulative dielectric interfacesuitable to fully deplete in an off-state; a gate contact applying agate voltage bias to control charge carrier accumulation and depletionin said channel portion; and the source dopant, the drain dopant, andthe channel portion dopant being all of a same type; and wherein thefirst ohmic contact interface is non-contiguous with said channelportion and the source linear extent, the drain linear extent, and thepositioning of the first ohmic contact interface and the second ohmiccontact interface prevent ambipolar behavior in the device.
 12. Thedevice of claim 11 wherein the doping type is p-type and the gatevoltage bias is negative and the drain voltage bias is negative to yielda device on-state status.
 13. The device of claim 11 wherein the dopingtype is p-type and the gate voltage bias is positive and the drainvoltage bias is negative to yield a device off-state status.
 14. Thedevice of claim 11 wherein the doping type is n-type and the gatevoltage bias is positive and the drain voltage bias is positive to yielda device on-state status.
 15. The device of claim 11 wherein the dopingtype is n-type and the gate voltage bias is negative and the drainvoltage bias is positive to yield a device off-state status.
 16. Thedevice of claim 11 wherein the dimension of said channel region normalto the gate is between 5 and 100 nanometers.
 17. The device of claim 11wherein said channel portion is formed from organic semiconductors orinorganic semiconductors.
 18. The device of claim 11 further comprisinga second gate intermediate between said source and the semiconductingdrain.
 19. The device of claim 11 wherein the channel portion is formedfrom one of: silicon, germanium, II-V1 semiconductors, III-Vsemiconductors, or carbon.